It is generally recognized that integrated circuits are susceptible to damage from electrostatic discharge (ESD). Such damage generally occurs when current and/or voltage ratings of devices in an integrated circuit are exceeded. Progress in VLSI technology today has resulted in smaller and smaller integrated circuit geometries in integrated circuits. With scaled-down device dimensions, shallow junction depths, thinner gate oxides, lightly doped drain (LDD) structures, and the use of salicide process technology, integrated circuits generally become more susceptible to ESD damage. This becomes more severe when the integrated circuit consists of multiple independently-powered circuit sections (e.g., sections of the integrated circuit having isolated power rails).
The Human Body Model (HBM) is a commonly used model for characterizing the susceptibility of an electronic device to damage from ESD. The model is a simulation of the discharge which might occur when a human touches an electronic device. The Machine Model (MM) is an alternative ESD model representing a discharge similar to the HBM event from a charged conductive object, such as a metallic tool or fixture. The Charged Device Model, in contrast, represents a transfer of charge from an ESD protection device. A CDM event can be more destructive than an HBM event for some devices. Although the duration of the discharge is very short (e.g., often less than one nanosecond) the peak current can reach several tens of amperes. Generally, the ESD robustness of integrated circuit devices should exceed 2 kV for HBM ESD events, 200V for MM events, and/or 500V for CDM events. It is often desirable to design integrated circuits that can satisfy these requirements with some margin of safety.
In advanced VLSI integrated circuit devices, power lines may be separated to avoid noise coupling and to reduce ground bouncing for high-performance circuit operation. However, it has been shown that integrated circuits with separated power pins and separated power lines may be more sensitive to ESD damage. For example, FIG. 1 shows a conventional ESD protection scheme in a mixed signal integrated circuit 100. Circuit 100 includes independently-powered circuit sections (e.g., input/output circuits) 110 and 140. Each circuit 110 and 140 has separate power lines. For example, circuit 110 includes first independent positive power rail (VDDIO_I) 111 and first independent negative power rail (VSSIO_I) 112. Similarly, circuit 140 has second independent positive power rail (VDDIO_II) 141 and second independent negative power rail (VSSIO_II) 142. Circuits 110 and 140 may receive their power from pads 113, 115, 143, and 145 (e.g., pins or ball bond for coupling to a power source that is external to the integrated circuit).
Each independently-powered circuit in this example has its own ESD protection devices in I/O buffers, RC shunts in power and ground pads, diodes and back-to-back diodes. The combination of ESD devices generally forms a complete route to shunt ESD current away from internal circuits during an ESD event. For example, in circuit 110 bond pads 113, 114, and 115 each represent a single I/O, power, or ground pad. For I/O pad 114, an output transistor (Mn_I) 116 and driver transistor (Mp_I) 117 act as ESD protection devices. Driver transistor 117 has its gate pulled high, drain coupled to I/O pad 114, and source and bulk both tied to the local power line 111. Output transistor 116 has its gate pulled low, drain coupled to I/O pad 114, and source and bulk both tied to local power line 112. Output transistor 116 thus forms a drain-bulk diode coupled between I/O pad 114 and negative power rail (VSSIO) 112, and driver transistor 117 forms a drain-bulk diode coupled between I/O pad 114 and positive power rail (VDDIO) 111. These two diodes also conduct current during ESD event. Some implementations may include additional ESD diodes 117 and 118. Output transistor 116 may commonly comprise a grounded gate NMOS (GGNMOS), also configured to be a breakdown device. The drain, bulk and source regions of output transistor 116 may form a bipolar junction transistor (BJT) device.
During an ESD event, the parasitic BJT may turn on and shunt the current to its source, in this case the negative power rail 112. Generally, a well-designed breakdown device will, during an ESD event, shunt the current sooner than a PFET transistor as long as the power lines are floating. This generally occurs because the gain of an n-type transistor is greater than a p-type transistor due to the lower diffusitivity of holes in NMOS. However, for simplicity, both GGNMOS 116 and ESD diodes 117 and 118 are shown in FIG. 1. I/O pad 144 of independently-powered circuit 140 has similar protection.
The independently-powered circuits also generally have ESD protection for each power and/or ground pad. For example, in independently-powered circuit 110, power pad 113 and ground pad 115 have RC-triggered shunt devices 119 and 120 across power lines 111 and 112. RC shunt devices 119 and 120 generally provide a low impedance path for ESD current to be shunted away from positive power rail (VDDIO) 111 to negative power rail (VSSIO) 112.
Referring now to FIG. 2, a detailed RC shunt device 120 is shown. During an ESD event, the RC circuitry generally pulls the intermediate node 123 low and in turn biases the gate of transistor 122. Transistor 122 is typically an NMOS device having total device width (W) of more than 1000 μm. When the gate of transistor 122 is biased at a voltage above a certain threshold, the transistor will turn on and create a short between power lines 111 and 112 to shunt the ESD current. Many factors must be considered when designing an RC-triggered shunt circuit. The combination of resistor 121 and capacitor 124 generally determines the period during which the RC shunt will be active during an ESD event. However, resistor 121 and capacitor 124 must also be selected such that, during normal operation (e.g., in the absence of an ESD event), the voltage at node 123 is high enough to keep inverter 125 tied low, so that transistor 122 remains turned off. Typical RC shunt delays are in the range of 1 to 5 micro-seconds (μs). The delay has much different magnitude from the rate of power ramping, which usually falls in the millisecond (ms) range. Accordingly, a circuit designer would not configure the RC shunt to have a delay near the millisecond range, to avoid a false triggering of the RC shunt device during a ramp of the power supply. Furthermore, in inverter 125 a PFET transistor 126 is generally much larger than the NFET transistor 127, in order to facilitate fast activation of the shunt device 120 when an ESD event occurs.
An ESD event may occur across any two pins in an IC device (e.g., whether they are input, output, power or ground pins). For example, an ESD event may occur between I/O pad 114 and I/O pad 144 of FIG. 1, with a positive charge at I/O pad 114 and a negative charge at I/O pad 144. A low impedance path must exist to shunt the ESD current away from the internal circuits (e.g., internal circuits 130 and 160) in order to avoid damage resulting from the ESD event. Generally, the ESD protection scheme shown in FIG. 1 employs power busses such as global positive power rail (VDD) 101 and independent positive power rails (VDDIO) 111 and 141, and ground busses such as global negative power rail (VSS) 102 and independent negative power rails (VSSIO) 112 and 142, to carry the ESD current. In this event, an ESD current enters the circuit at I/O pad 114 and flows through diode 117 to power line 111. The sudden change of voltage at power line 111 will trigger the RC shunts 119 and 120 to create a substantially instantaneous short between power line 111 and ground line 112. The ESD current then flows through this less resistive path created by the sudden short from power line 111 to ground line 112. The ESD current may then flow from independent ground line 112 to global ground line 102 through back-to-back diodes 103, then from the global ground line 112 to second independent ground line 142 in independently-powered circuit 141. The ESD current may then complete the circuit by flowing through diode 148 to I/O pad 144, where the ESD current exits the chip.
In order to protect the internal circuit from ESD damage, the voltage drops along the ESD current carrying path should be maintained below a breakdown voltage Vbreakdown of the gate oxide and silicon junctions of the devices in the path. The total voltage drop for the above-described ESD event between I/O pad 114 and I/O pad 144 is the sum of the threshold voltages for entering diode 118 and exiting diode 148 (typically 0.7V each), IR voltage drops across the RC shunt devices (typically 6V), threshold voltage for back-to-back diode 103 (typically 0.7V each) and the IR voltage drop across power supply and ground substrates when the ESD current flows through the parasitic resistance at the power busses.
Usually the global positive power rail (VDD) 101 and the global negative power rail (VSS) 102 busses are configured as a continuous ring around the IC. Therefore, the total protection of devices across global power lines is the sum of all the shunt devices connected to the VDD and VSS power ring. This raises the threshold for ESD damage to occur across VDD and VSS. However, as shown in FIG. 1, there are cases where the chip may be separated into independently-powered circuits (e.g., because some parts of the chip require “clean” power supplies, some of the supplies have low noise immunity, and some power supplies generate noise during normal operation, especially clock pins connected to an external power supply).
By separating power lines, noise coupling and other problems as described above can be reduced. However, separating the power lines may reduce protection from ESD events. Mixed signal integrated circuits having multiple independent power lines may be more susceptible to ESD damage, especially in sections of the integrated circuit where few power pads are used. As shown above, RC-triggered shunt devices (e.g., RC shunt device 120 of FIG. 2) are generally coupled to power pads (e.g., power pads 113 and 115). Thus, when there are relatively few power pads in a section, there is generally less capacity for shunting ESD current from supply to ground.
Referring now to FIG. 3, integrated circuit 300, having independently-powered sections 310 (Section I), 320 (Section II), and 330 (Section III), is shown. Independently-powered section 310 has multiple I/O pads 311, multiple power (VDDIO) pads 312, and multiple ground (VSSIO) pads 313. Thus, section 310 is generally adequately protected because the multiple power pads provide multiple RC shunt devices 314 and 315 in parallel, facilitating the shunting of an ESD current when an ESD event occurs at I/O pads 311.
Independently-powered section 320 has only one I/O pad 321 accompanied by one power pad 322 and one ground pad 323. Thus, in independently-powered section 320, there may be only two RC shunt devices 326 and 327 connecting power line 324 and ground line 325. Any ESD current that enter at I/O pad 321 would flow through diode 378 to power line 324, then trigger RC shunt devices 326 and 327 to shunt the ESD current to ground line 325. By having multiple RC shunts as in sections 310 and 330, the IC can surpass HBM 2 kV requirements, because multiple parallel shunts may activate at substantially the same time to shunt the ESD current. This reduces the IR voltage drops across the shunts by 30% to 50% compared to the 2 RC shunt devices 326 and 327 in section 320. Thus, section 320 is relatively susceptible to ESD damage because it has a relatively high total IR voltage drop (e.g., because it has fewer parallel RC shunt devices), so that the total voltage drop is more likely to exceed Vbreakdown.
One solution to this problem is to add multiple power pads to a section to increase the section's protection from ESD events. However, as integrated circuit technology progresses with decreasingly small scales, such an approach may require 10 or more power and ground pads to protect one or two isolated I/O pads. Thus, this approach becomes increasingly impractical as it consumes relatively large areas of a semiconductor die, increasing the cost of manufacturing the integrated circuit devices.
Therefore, it may be beneficial or advantageous to protect integrated circuits having independently-powered circuit sections from electrostatic discharge events without adding redundant power and/or ground pads.